1. Field of the Invention
The present invention relates to a pulse output circuit, a shift register and a display device.
2. Description of the Related Art
In recent years, a display device in which a circuit is formed on an insulating substrate, specifically on a glass or plastic substrate, by using thin film transistors (hereinafter referred to as TFTs) formed of a semiconductor thin film has been developed. Specifically, development of an active matrix display device has been remarkably advanced. The active matrix display device formed of TFTs includes hundred thousands to millions of pixels which are arranged in matrix, and the TFTs provided in each pixel control the charge of each pixel to display an image.
Further, polysilicon TFTs which have excellence in electrical properties have been developed instead of amorphous TFTs. By using the polysilicon TFTs, a method of forming a driver circuit in the periphery of a pixel portion simultaneously with a pixel TFT constituting a pixel has been developed as a recent technology. The method makes a significant contribution to reduction in size, weight and power consumption of the device, therefore, it is becoming an essential technology for forming the display portion of a portable information terminal or the like whose application fields are remarkably expanding in recent years.
In general, a CMOS circuit which is formed with the combination of an N-type TFT and a P-type TFT is used for a circuit constituting a driver circuit of the display device. The CMOS circuit is characterized in that there is a current flow only when the logic is inverted (from High level to Low level or from Low level to High level), and ideally, there is no current flow while retaining certain data (practically, there is a small amount of leak current flow). Therefore, the CMOS circuit has the advantage of being cable of reducing power consumption considerably in the whole circuit and of operating at high speed because the P-type TFT and the N-type TFT complement each other
However, as for the manufacturing step of the CMOS circuit, the number of steps is increased due to the complicated steps of ion doping or the like, and thus, it is difficult to reduce the production cost. Consequently, a circuit which is formed of TFTs of a single conductivity type, that is, either of N-type TFTs or P-type TFTs, and is capable of operating at as high speed as a CMOS circuit has been proposed instead of a conventional circuit formed of a CMOS circuit (see Patent Document 1, for example).
According to a circuit disclosed in Patent Document 1, as shown in FIGS. 2A to 2C, a gate electrode of a TFT 205 connected to an output terminal is made temporarily in a floating state, and by using capacitive coupling between a gate and source of the TFT 205, the potential of the gate electrode can be made higher than a power source potential. As a result, an output without amplitude attenuation can be obtained without causing a voltage drop due to a threshold voltage of the TFT 205.
Such operation in the TFT 205 is known as a bootstrap operation. This operation facilitates the output of pulse without causing a voltage drop due to a threshold voltage of the TFT.
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-335153
With reference to a pulse output circuit shown in FIG. 2B, a potential of an output node is focused. FIG. 2C shows operation timing of a shift register shown in FIG. 2A. During a period in which no pulse is inputted and outputted, potentials of input terminals 2 and 3 in the pulse output circuit shown in FIG. 2B are Low level, that is, TFTs 201 to 204 are all turned OFF. As a result, gate electrodes of the TFT 205 and a TFT 206 both become in a floating state.
At this time, either a clock signal CK 1 or a clock signal CK 2 is inputted to an input terminal 1, namely a drain region of the TFT 205 which corresponds to a first electrode of the TFT 205 (as to source and drain regions of the TFT 205, a lower potential part is referred to as a source region and a higher potential part is referred to as a drain region herein). Due to a capacitive coupling with the drain region, the potential of the gate electrode of the TFT 205 which is in a floating state, namely a potential of a node xcex1 is varied as noise in accordance with a clock signal as shown in FIG. 2C with a reference numeral 250.
This variation in potential is much smaller as compared with pulses with normal amplitude, therefore, it is not so serious when a power source voltage (potential difference between VDD and VSS) is sufficiently large. That is, there is few possibility of the malfunction of the TFT 205 caused by the variation in potential such as noise. However, the TFT 205 is likely to malfunction in the case of adopting a low voltage operation to reduce power consumption or the like.
In view of the foregoing, it is the primary object of the invention to provide a pulse output circuit and a shift register which are capable of reducing the noise in a circuit and operating more accurately.
To solve the above-described problems, the following measures are taken in the invention.
One of the reasons why the potential is varied as noise during a period in which there is no output of pulse is that both the TFTs 205 and 206 are in a floating state and a signal having amplitude such as a clock signal is inputted to the drain region of the TFT 205.
Therefore, according to the invention, a TFT such as the TFT 205 to which is inputted a signal having amplitude such as a clock signal is configured so as to be fixed its ON or OFF during a period in which there is no output of pulse.
It is to be noted that in this specification, it is defined that a display device includes a liquid crystal display device in which liquid crystal elements are used as pixels and a display device in which self-luminous elements such as electro luminescence (EL) elements are used as pixels. It is also defined that a driver circuit of the display device is a circuit for inputting an image signal into a pixel disposed in the display device to carry out a step of displaying an image and includes a pulse output circuit such as shift register and inverter and an amplification circuit such as amplifier.
A pulse output circuit according to the invention comprises:
first to third input terminals;
an output terminal;
a first transistor including a first electrode electrically connected to the first input terminal;
a second transistor including a first electrode electrically connected to a power source;
a first amplitude compensation circuit;
a second amplitude compensation circuit; and
a capacitance means,
and in the pulse output circuit according to the invention:
channel regions of first and second transistors have a same conductivity type;
each of a second electrode of the first transistor and a second electrode of the second transistor is electrically connected to the output terminal;
the capacitance means is provided between a gate electrode of the first transistor and the second electrode of the first transistor;
the gate electrode of the first transistor is electrically connected to an output terminal of the first amplitude compensation circuit;
a gate electrode of the second transistor is electrically connected to an output terminal of the second amplitude compensation circuit;
the second input terminal is electrically connected to each of a first input terminal of the first amplitude compensation circuit and a first input terminal of the second amplitude compensation circuit;
the third input terminal is electrically connected to a second input terminal of the second amplitude compensation circuit; and
the output terminal of the second amplitude compensation circuit is electrically connected to a second input terminal of the first amplitude compensation circuit.
An output circuit according to the invention comprises:
first to third input terminals;
an output terminal;
a first transistor including a first electrode electrically connected to the first input terminal;
a second transistor including a first electrode electrically connected to a power source;
a first amplitude compensation circuit;
a second amplitude compensation circuit;
a capacitance means; and
a scanning direction switch circuit,
and in the pulse output circuit according to the invention:
channel regions of the first and second transistors have a same conductivity type;
each of a second electrode of the first transistor and a second electrode of the second transistor is electrically connected to the output terminal;
the capacitance means is provided between a gate electrode of the first transistor and the second electrode of the first transistor,
the gate electrode of the first transistor is electrically connected to an output terminal of the first amplitude compensation circuit;
a gate electrode of the second transistor is electrically connected to an output terminal of the second amplitude compensation circuit;
the second input terminal is electrically connected to a first input terminal of the first amplitude compensation circuit and to either a first input terminal of the second amplitude compensation circuit or a second input terminal of the second amplitude compensation circuit via the scanning direction switch circuit;
the third input terminal is electrically connected to the input terminal of the first amplitude compensation circuit and to either the first input terminal of the second amplitude compensation circuit or the second input terminal of the second amplitude compensation circuit via the scanning direction switch circuit;
the output terminal of the second amplitude compensation circuit is electrically connected to a second input terminal of the first amplitude compensation circuit;
when the scanning direction switch circuit is in a first state, a signal inputted to the second input terminal is inputted to each of the first input terminal of the first amplitude compensation circuit and the first input terminal of the second amplitude compensation circuit, and a signal inputted to the third input terminal is inputted to the second input terminal of the second amplitude compensation circuit; and
when the scanning direction switch circuit is in a second state, a signal inputted to the second input terminal is inputted to the second input terminal of the second amplitude compensation circuit, and a signal inputted to the third input terminal is inputted to each of the first input terminal of the first amplitude compensation circuit and the first input terminal of the second amplitude compensation circuit.
A pulse output circuit according to the invention comprises:
first to fourth input terminals;
an output terminal;
a first transistor including a first electrode electrically connected to the first input terminal;
a second transistor including a first electrode electrically connected to a first power source;
a third transistor including a first electrode electrically connected to a second power source;
first and second amplitude compensation circuits; and
a capacitance means,
and in the pulse output circuit according to the invention:
channel regions of all the first, second and third transistors have a same conductivity type;
each of a second electrode of the first transistor and a second electrode of the second transistor is electrically connected to the output terminal;
the capacitance means is provided between a gate electrode of the first transistor and the second electrode of the first transistor;
the gate electrode of the first transistor is electrically connected to an output terminal of the first amplitude compensation circuit;
a gate electrode of the second transistor is electrically connected to an output terminal of the second amplitude compensation circuit;
the second input terminal is electrically connected to each of a first input terminal of the first amplitude compensation circuit and a first input terminal of the second amplitude compensation circuit;
the third input terminal is electrically connected to a second input terminal of the second amplitude compensation circuit;
the output terminal of the second amplitude compensation circuit is electrically connected to a second input terminal of the first amplitude compensation circuit.
the fourth input terminal is electrically connected to a gate electrode of the third transistor; and
a second electrode of the third transistor is electrically connected to the gate electrode of the second transistor.
A pulse output circuit according to the invention comprises:
first to third input terminals;
an output terminal;
a first transistor including a first electrode electrically connected to the first input terminal;
a second transistor including a first electrode electrically connected to a first power source;
a third transistor including a first electrode electrically connected to a second power source or a gate electrode thereof;
a fourth transistor including a first electrode electrically connected to the first power source;
a fifth transistor including a first electrode electrically connected to the second power source;
a sixth transistor including a first electrode electrically connected to the first power source; and
a capacitance means,
and in the pulse output circuit according to the invention:
channel regions of all the first to sixth transistors have a same conductivity type;
each of a second electrode of the first transistor and a second electrode of the second transistor is electrically connected to the output terminal;
the capacitance means is provided between a gate electrode of the first transistor and the second electrode of the first transistor;
each of a second electrode of the third transistor and a second electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;
each of a second electrode of the fifth transistor and a second electrode of the sixth transistor is electrically connected to a gate electrode of the second transistor and to a gate electrode of the fourth transistor;
each of a gate electrode of the third transistor and a gate electrode of the sixth transistor is electrically connected to the second input terminal; and
a gate electrode of the fifth transistor is electrically connected to the third input terminal.
The above-mentioned pulse output circuit may comprise a seventh transistor, and the seventh transistor may include a gate electrode electrically connected to the second power source and be provided between an output electrode of the third transistor and the gate electrode of the first transistor.
The above-mentioned pulse output circuit may comprise:
a seventh transistor including a first electrode connected to a gate electrode thereof; and
an eighth transistor including a first electrode electrically connected to the first power source,
and in the pulse output circuit according to the invention:
the seventh transistor may be provided between the output electrode of the third transistor and the gate electrode of the first transistor; and
a gate electrode of the eighth transistor may be electrically connected to each of the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a second electrode of the eighth transistor may be electrically connected to the gate electrode of the first transistor.
A pulse output circuit comprises:
first to third input terminals;
an output terminal;
a first transistor including a first electrode electrically connected to the first input terminal;
a second transistor including a first electrode electrically connected to a first power source;
a third transistor including a first electrode electrically connected to a second power source or a gate electrode thereof;
a fourth transistor including a first electrode electrically connected to the first power source;
a fifth transistor including a first electrode electrically connected to the second power source;
a sixth transistor including a first electrode electrically connected to the first power source;
a capacitance means; and
a scanning direction switch circuit,
and in the pulse output circuit according to the invention:
channel regions of all the first to sixth transistors have a same conductivity type;
each of a second electrode of the first transistor and a second electrode of the second transistor is electrically connected to the output terminal;
the capacitance means is provided between a gate electrode of the first transistor and the second electrode of the first transistor;
each of a second electrode of the third transistor and a second electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;
each of a second electrode of the fifth transistor and a second electrode of the sixth transistor is electrically connected to a gate electrode of the second transistor and to a gate electrode of the fourth transistor;
each of a gate electrode of the third transistor and a gate electrode of the sixth transistor is electrically connected to the second input terminal or the third input terminal via the scanning direction switch circuit;
a gate electrode of the fifth transistor is electrically connected to the second input terminal or the third input terminal via the scanning direction switch circuit;
when the scanning direction switch circuit is in a first state, a signal inputted to the second input terminal is inputted to each of the gate electrode of the third transistor and the gate electrode of the sixth transistor, and a signal inputted to the third input terminal is inputted to the gate electrode of the fifth transistor; and
when the scanning direction switch circuit is in a second state, a signal inputted to the second input terminal is inputted to the gate electrode of the fifth transistor, and a signal inputted to the third input terminal is inputted to each of the gate electrode of the third transistor and the gate electrode of the sixth transistor.
The above-mentioned pulse output circuit may comprise a seventh transistor, and the seventh transistor may include a gate electrode electrically connected to the second power source and be provided between the output electrode of the third transistor and the gate electrode of the first transistor.
The above-mentioned pulse output circuit may comprise:
a seventh transistor including a first electrode connected to a gate electrode thereof; and
an eighth transistor including a first electrode electrically connected to the first power source,
and in the pulse output circuit according to the invention:
the seventh transistor may be provided between an output electrode of the third transistor and the gate electrode of the first transistor; and
a gate electrode of the eighth transistor may be electrically connected to each of the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a second electrode of the eighth transistor may be electrically connected to the gate electrode of the first transistor.
A pulse output circuit according to the invention comprises:
first to fourth input terminals;
an output terminal;
a first transistor including a first electrode electrically connected to the first input terminal;
a second transistor including a first electrode electrically connected to a first power source;
a third transistor including a first electrode electrically connected to a second power source or a gate electrode thereof;
a fourth transistor including a first electrode electrically connected to the first power source;
a fifth transistor including a first electrode electrically connected to the second power source;
a sixth transistor including a first electrode electrically connected to the first power source;
a seventh transistor including a first electrode electrically connected to the second power source; and
a capacitance means,
and in the pulse output circuit according to the invention:
channel regions of all the first to seventh transistors have a same conductivity type;
each of a second electrode of the first transistor and a second electrode of the second transistor is electrically connected to the output terminal;
the capacitance means is provided between a gate electrode of the first transistor and the second electrode of the first transistor;
each of a second electrode of the third transistor and a second electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;
each of a second electrode of the fifth transistor, a second electrode of the sixth transistor and a second electrode of the seventh transistor is electrically connected to a gate electrode of the second transistor and to a gate electrode of the fourth transistor;
each of a gate electrode of the third transistor and a gate electrode of the sixth transistor is electrically connected to the second input terminal;
a gate electrode of the fifth transistor is electrically connected to the third input terminal; and
a gate electrode of the seventh transistor is electrically connected to the fourth input terminal.
The above-mentioned pulse output circuit may comprise an eighth transistor, and the eighth transistor may include a gate electrode electrically connected to the second power source and be provided between an output electrode of the third transistor and the gate electrode of the first transistor.
The above-mentioned pulse output circuit may comprise:
an eighth transistor including a gate electrode electrically connected to a first electrode thereof; and
a ninth transistor including a first electrode electrically connected to the first power source,
and in the pulse output circuit according to the invention:
the eighth transistor may be provided between the output electrode of the third transistor and the gate electrode of the first transistor; and
a gate electrode of the ninth transistor may be electrically connected to each of the gate electrode of the second transistor and the gate electrode of the fourth transistor, and a second electrode of the ninth transistor may be electrically connected to the gate electrode of the first transistor.
According to the invention, a capacitance between the gate electrode and the second electrode of the first transistor may be used as the capacitance means.
According to the invention, a capacitance formed of first and second films each comprising either one of an active layer material, a gate electrode material and a wiring material, and of an insulating film provided between the first and second films may be used as the capacitance means.
A shift register is provided for example by using a plurality of stages of a pulse output circuit of the invention.